Analog-to-digital converters (ADCs) frequently are used to digitize an analog signal. In many implementations, the analog signal may vary significantly and thus the ADC must have a wide input range. This wide input range poses a problem with respect to conversion accuracy for conventional ADCs. A conventional ADC can be designed with higher number of conversion bits to achieve a desired conversion accuracy, but at the expense of increased complexity, increased silicon area, and increased power consumption. Conversely, a conventional ADC can be designed with a lower number of conversion bits with the benefits of decreased complexity, decreased silicon area, and decreased power consumption, but at the expense of conversion accuracy.